Automatically assigned DDC number: 00422

Manually assigned DDC number: 00466

Number of references: 0

Title: Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control

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Subject: George Kornaros,Christoforos Kozyrakis,Panagiota Vatsolaki,Manolis Katevenis Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control

Description: : We describe the queue management block of ATLAS I , a single-chip ATM switch (router) with optional credit-based (backpressure) flow control. ATLAS I is a 4-million-transistor 0.35-micron CMOS chip, currently under development, offering 20 Gbit/s aggregate I/O throughput, sub-microsecond cut-through latency, 256-cell shared buffer containing multiple logical output queues, priorities, multicasting, and load monitoring. The queue management block of ATLAS I is a dual parallel pipeline that manages the multiple queues of ready cells, the per-flow-group credits, and the cells that are waiting for credits. All cells, in all queues, share one, common buffer space. These 3- and 4-stage pipelines handle events at the rate of one cell arrival or departure per clock cycle, and one credit arrival per clock cycle. The queue management block consists of two compiled SRAM's, pipeline bypass logic, and multi-port CAM and SRAM blocks that are laid out in full-custom and support special access Cop...

Contributor: The Pennsylvania State University CiteSeer Archives

Publisher: unknown

Date: 1997-08-19

Pubyear: 1997

Format: ps

Identifier: http://citeseer.ist.psu.edu/140749.html

Source: http://www.ics.forth.gr/proj/arch-vlsi/papers/1997.ARVLSI.Pipe_MultiQueue.ps.gz

Language: en

Rights: unrestricted